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| DARPA | Microsystems | Budget Code: | ST-19 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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This activity is responsible for the science and technology that enable the design, development, manufacture, and application of advanced microsystems from basic research through small-scale prototyping. Microsystems refers to integrated components that enable innovative computing systems. A key focus is high performance, densely packaged, low power, scalable components that can be accurately simulated, realized in advanced implementation technologies, and rapidly designed into candidate architectures. Technology investments include tools, techniques, and algorithms enabling design of complex digital microsystems, the application of scalable computing and communications technology to accelerate system design, the creation of distributed virtual research and design concepts supporting the broad hierarchy of digital design from integrated circuit processes to complex computing systems, and architectural exploration leading to the creation of fundamental scalable components for next generation HPC and Embeddable HPC systems.
Design Technology provides the CAD tools and environments to support the program goals of Microsystems. Specifically, Design Technology focuses on simulation, synthesis, co-design, verification, dependability, and testability of complex digital electronic systems. Computational Prototyping exploits the HPC technology base to enable and accelerate design verification, modeling, simulation, synthesis, and testing of complex digital systems. Microarchitectures explores innovative microarchitectural concepts and fundamentally new models of computing through small-scale experiments. These experiments provide a vehicle for innovative leading edge, university-based architectural investigation to develop and prove new approaches. These early validations of architectural concepts provide the basis of future larger-scale HPC efforts. |
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Demonstrated derivation of electrical parameters from 3-D process models using early computational prototyping methods.
Demonstrated prototype secure distributed design environment for electronic systems. Initial demonstration of microarchitectures for advanced packaging and scalable units of replication. Demonstrated scalable, high performance, low-latency switch technology for workstation clusters. |
Perform early demonstration of parallel, fully-hierarchical Automatic Test Generation for both combinational and sequential circuits.
Demonstrate fault-tolerant and reliability design tools supporting large-scale HPC systems developments. Demonstrate message-passing/shared-memory hybrid architecture protocol accelerator component. Demonstrate distributed computing architectures based on low-cost, low-latency switching technology. Prototype emulation-enhanced system simulation capabilities for microsystem design. Demonstrate integrated module-level synthesis capability. |
Demonstrate high-level, portable parallel test generation system.
Develop fully-integrated, parameterized, constraint-driven design libraries. Demonstrate initial multisite collaborative design research environment for integrated circuit process simulation and remote experimentation over the NII. Demonstrate distributed shared memory components on cluster of workstations. |
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